Board Components
Table 2–6 shows all connections between the FPGA and the SSRAM chip.
Table 2–6. SSRAM Pin Table
AB3
AB4
G5
G6
B2
B3
C2
C3
L9
F7
L10
J5
L4
C6
A4
B4
A5
B5
B6
A6
C4
G9
M3
M2
M4
M5
C7
L2
L3
L7
L6
N9
FPGA Pin
37
36
35
34
33
32
38
39
42
43
44
45
46
47
48
49
50
81
82
99
100
85
93
94
95
96
98
52
53
56
57
58
U74 Pin
Pin Function
A0
A1
A2
A3
A4
A5
NC/A19
NC/A20
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
ADSC_N
BE_n0
BE_n1
BE_n2
BE_n3
CE1_n
D0
D1
D2
D3
D4
Board Net Name
ssram_a0
ssram_a1
ssram_a2
ssram_a3
ssram_a4
ssram_a5
ssram_a6
ssram_a7
ssram_a8
ssram_a9
ssram_a10
ssram_a11
ssram_a12
ssram_a13
ssram_a14
ssram_a15
ssram_a16
ssram_a17
ssram_a18
ssram_a19
ssram_a20
ssram_adsc_n
ssram_be_n0
ssram_be_n1
ssram_be_n2
ssram_be_n3
ssram_ce1_n
ssram_d0
ssram_d1
ssram_d2
ssram_d3
ssram_d4
Altera Corporation
May 2007
Reference Manual 2–7
Nios Development Board Cyclone II Edition
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